differential clock buffer/drive r ddr400/pc3200-compliant cy2sstv857-32 cypress semiconductor corporation ? 3901 north first street ? san jose , ca 95134 ? 408-943-2600 document #: 38-07557 rev. *d revised august 24, 2004 features ? operating frequency: 60 mhz to 230 mhz ? supports 400-mhz ddr sdram ? 10 differential outputs from one differential input ? spread-spectrum-compatible ? low jitter (cycle-to-cycle): < 75 ? very low skew: < 100 ps ? power management control input ? high-impedance outputs when input clock < 20 mhz ? 2.6v operation ? pin-compatible wit h cdc857-2 and -3 ? 48-pin tssop and 40 qfn package ? industrial temperature of ?40c to 85c ? conforms to jedec ddr specification description the cy2sstv857-32 is a high-performance, low-skew, low-jitter zero-delay buffer designed to distribute differential clocks in high-speed applications. the cy2sstv857-32 generates ten differential pair clock outputs from one differ- ential pair clock input. in addition, the cy2sstv857-32 features differential feedback clock outputs and inputs. this allows the cy2sstv857-32 to be used as a zero delay buffer. when used as a zero delay buffer in nested clock trees, the cy2sstv857-32 locks onto the i nput reference and translates with near-zero delay to low-skew outputs. block diagram pin configuration 3 2 5 6 10 9 20 19 22 23 46 47 44 43 39 40 29 30 27 26 32 33 y0 y0# y1 y1# y2 y2# y3 y3# y4 y4# y5 y5# y6 y6# y7 y7# y8 y8# y9 y9# fbout fbout# test and powerdown logic pll 13 14 36 35 fbin fbin# clk clk# avdd 37 16 pd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 vss y0# y0 vddq y1 y1# vss vss y2# y2 vddq vddq clk clk# vddq avdd avss vss y3# y3 vddq y4 y4# vss 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 vss y5# y5 vddq y6 y6# vss vss y7# y7 vddq pd# fbin fbin# vddq fbout# fbout vss y8# y8 vddq y9 y9# vss cy2sstv857-32 48 tssop package
cy2sstv857-32 document #: 38-07557 rev. *d page 2 of 9 pin description pin # 48 tssop pin # 40 qfn pin name i/o [1] pin description electrical characteristics 13, 14 5,6 clk, clk# i differential clock input . lv differential input 35 25 fbin# i feedback clock input . connect to fbout# for accessing the pll. differential input 36 26 fbin i feedback clock input . connect to fbout for accessing the pll. 3, 5, 10, 20, 22 37, 39,3,12,14 y(0:4) o clock outputs . differential outputs 2, 6, 9, 19, 23 36,40,2,11,15 y#(0:4) o clock outputs . 27, 29, 39, 44, 46 17,19,29,32,34 y(9:5) o clock outputs . differential outputs 26, 30, 40, 43, 47 16,20,30,31,35 y#(9:5) o clock outputs . 32 21 fbout o feedback clock output . connect to fbin for normal operation. a bypass delay capacitor at this output will control input reference/output clocks phase relationships. differential outputs 33 22 fbout# o feedback clock output . connect to fbin# for normal operation. a bypass delay capacitor at this output will control input reference/output clocks phase relationships. 37 27 pd# i power down input . when pd# is set high, all q and q# outputs are enabled and switch at the same frequency as clk. when set low, all q and q# outputs are disabled hi-z and the pll is powered down. 4, 11,12,15, 21, 28, 34, 38, 45 4,7,13,18,23,24, 28,33,38 vddq 2.6v power supply for output clock buffers . 2.6v nominal 16 8 avdd 2.6v power su pply for pll . when vdda is at gnd, pll is bypassed and clk is buffered di- rectly to the device outputs. during disable (pd# = 0), the pll is powered down. 2.6v nominal 1, 7, 8, 18, 24, 25, 31, 41, 42, 48 1,10 vss common ground . 0.0v ground 17 9 avss analog ground . 0.0v analog ground note: 1. a bypass capacitor (0.1 f) should be placed as close as possible to each positive power pin (<0.2?). if these bypass capacitors are not close to the pi ns, their high-frequency filtering characteristic will be ca ncelled by the lead inductance of the traces. 40 qfn cy2sstv857-32 19 18 17 16 15 14 13 12 11 20 y3# y3 vddq y4 y4# y9# y9 vddq y8 y8# 32 33 34 35 36 37 38 39 40 31 y1# y1 vddq y0 y0# y5# y5 vddq y6 y6# 30 29 28 27 26 25 24 23 22 21 y7# vddq y7 pd# fbin fbin# vddq vddq fbout# fbout 1 2 3 4 5 6 7 8 9 10 vss y2 y2# vddq clk clk# vddq avdd avss vss 40 qfn package
cy2sstv857-32 document #: 38-07557 rev. *d page 3 of 9 zero delay buffer when used as a zero delay buffer the cy2sstv857-32 will likely be in a nested clock tree application. for these applica- tions, the cy2sstv857-32 offers a differential clock input pair as a pll reference. the cy2s stv857-32 then can lock onto the reference and translate with near zero delay to low-skew outputs. for normal operation, the external feedback input, fbin, is connected to the feedback output, fbout. by connecting the feedback output to the feedback input the propagation delay through the device is eliminated. the pll works to align the output edge with the input reference edge thus producing a near zero delay. the reference frequency affects the static phase offset of the pll and thus the relative delay between the inputs and outputs. when vdda is strapped low, the pll is turned off and bypassed for test purposes. power management output enable/disable control of the cy2sstv857-32 allows the user to implement power management schemes into the design. outputs are three-stated/disabled when pd# is asserted low (see table 1 ). table 1. function table inputs outputs pll avdd pd# clk clk# y y# fbout fbout# gnd h l h l h l h bypassed/off gnd h h l h l h l bypassed/off xllhzzzz off xlhlzzzz off 2.6v h l h l h l h on 2.6v h h l h l h l on 2.6v h < 20 mhz < 20 mhz hi-z hi-z hi-z hi-z off clkin t (phase error) fbin fbout t sk(o) yx yx yx t sk(o) figure 1. phase error and skew waveforms
cy2sstv857-32 document #: 38-07557 rev. *d page 4 of 9 clkin t pd yx or fbin figure 2. propagation delay time t plh , t phl t c(n+1) yx t c(n) figure 3. cycle -to-cycle jitter pll fbin fbin# 120 ohm 120 ohm clk clk# ddr - sdram 120 ohm vtr vcp 0.3" = 2.5" = 0.6" (split to terminator) ddr _sdram represents a capacitive load ddr - sdram fbout# fbout output load capacitance for 2 ddr-sdram loads: 5 pf< cl< 8 pf figure 4. clock structure # 1
cy2sstv857-32 document #: 38-07557 rev. *d page 5 of 9 clk clk# ddr-sdram pll fbin fbin# 120 ohm 120 ohm ddr-sdram stack ddr-sdram stack 120 ohm vtr vcp 0.3" = 2.5" = 0.6" (split to terminator) ddr-sdram represents a capacitive load fbout# fbout ddr-sdram ddr-sdram ddr-sdram output load capacitancce for 4 ddr-sdram loads: 10 pf < cl < 16 pf figure 5. clock structure # 1 60 ohm receiver vcp vtr r t = 120 ohm out out# vddq 60 ohm 14 pf 14 pf vddq/2 vddq/2 vddq figure 6. differential signal using direct termination resistor
cy2sstv857-32 document #: 38-07557 rev. *d page 6 of 9 absolute maximum conditions [2] input voltage relative to v ss :...............................v ss ? 0.3v input voltage relative to v ddq or av dd : ........... v ddq + 0.3v storage temperature: ............. .............. ..... ?65c to + 150c operating temperature: ................................ ?40c to +85c maximum power supply: ................................................3.5v this device contains circuitry to protect the inputs against damage due to high static voltages or electric field; however, precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. for proper operation, v in and v out should be constrained to the range: v ss < (v in or v out ) < v ddq . unused inputs must always be tied to an appropriate logic voltage level (either v ss or v ddq ). dc electrical specifications [3] parameter description condition min. typ. max. unit v ddq supply voltage operating 2.375 ? 2.625 v v il input low voltage pd# ? ? 0.3 v ddq v v ih input high voltage 0.7 v ddq ??v v id differential input voltage [4] clk, fbin 0.36 ? v ddq + 0.6 v v ix differential input crossing voltage [5] clk, fbin (v ddq /2) ? 0.2 v ddq /2 (v ddq /2) + 0.2 v i in input current [clk, fbin, pd#] v in = 0v or v in = v ddq ?10 ? 10 a i ol output low current v ddq = 2.375v, v out = 1.2v 26 35 ? ma i oh output high current v ddq = 2.375v, v out = 1v 28 ?32 ? ma v ol output low voltage v ddq = 2.375v, i ol = 12 ma ? ? 0.6 v v oh output high voltage v ddq = 2.375v, i oh = ?12 ma 1.7 ? ? v v out output voltage swing [6] 1.1 ? v ddq ? 0.4 v v oc output crossing voltage [7] (v ddq /2) ? 0.2 v ddq /2 (v ddq /2) + 0.2 v i oz high-impedance output current v o = gnd or v o = v ddq ?10 ? 10 a i ddq dynamic supply current [8] all v ddq , f o = 200 mhz ? 235 300 ma i dd pll supply current v dda only ? 9 12 ma i dds standby supply current pd# = 0 and clk/clk# = 0 mhz ? ? 100 a cin input pin capacitance 2 ? 3.5 pf ac electrical specifications [9, 10] parameter description condition min. typ. max. unit f clk operating clock frequency av dd , v ddq = 2.6v 0.1v 60 ? 230 mhz t dc input clock duty cycle 40 ? 60 % t lock maximum pll lock time ? ? 100 s d tyc duty cycle [11] 60 mhz to 100 mhz 49 50 51 % 101 mhz to 170 mhz 48 ? 52 % tsl(o) output clocks slew rate 20%?80% of vod 1 2 v/ns t pzl , t pzh output enable time [12] (all outputs) ? 3 25 ns t plz , t phz output disable time [12] (all outputs) ? 3 8 ns notes: 2. multiple supplies: the voltage on any input or i/o pin cannot exceed the power pin during power-up. power supp ly sequencing is not required. 3. unused inputs must be held high or low to prevent them from floating. 4. differential input signal voltage specifies the differential vo ltage vtr?vcpi required for switching, where vtr is the true i nput level and vcp is the complementary input level. see figure 6 . 5. differential cross-point input voltage is expected to track v ddq and is the voltage at which the differential signal must be crossing. 6. for load conditions see figure 6 . 7. the value of voc is expected to be (vtr + vcp)/2. in case of each clock directly terminated by a 120 ? resistor. see figure 6 . 8. all outputs switching load with 14 pf in 60 ? environment. see figure 6 . 9. parameters are guaranteed by design and char acterization. not 100% tested in production. 10. pll is capable of meeting the specified parameters while supporting ssc synthesizers with modulation frequency between 30 kh z and 50 khz with a down spread or ?0.5%. 11. while the pulse skew is almost consta nt over frequency, the duty cycle error in creases at higher frequencies. this is due to the formula: duty cycle = t whc /t c , where the cycle time(tc) decreas es as the frequency goes up. 12. refers to transition of non-inverting output.
cy2sstv857-32 document #: 38-07557 rev. *d page 7 of 9 notes: 13. period jitter and half-period jitter specifications are separate specifications that must be met independently of each other . 14. all differential input and output terminals are terminated with 120 ? /16 pf, as shown in figure 5 . 15. the ordering part number differs from the marking on the actual device. see figure 7 for the actual marking on the device. t ccj cycle to cycle jitter [10] f > 66 mhz ?75 ? 75 ps tjit(h-per) half-period jitter [10, 13] f > 66 mhz ?100 ? 100 ps t plh( t pd) low-to-high propagation delay, clk to y test mode only 1.5 3.5 7.5 ns t phl( t pd) high-to-low propagation delay, clk to y 1.5 3.5 7.5 ns t sk(o) any output to any output skew [14] ? ? 100 ps t phase phase error [14] ?50 ? 50 ps ordering information part number package type product flow cy2sstv857zc?32 48-pin tssop commercial, 0 to 70 c cy2sstv857zc?32t 48-pin tssop?tape and reel commercial, 0 to 70 c cy2sstv857lfc?32 [15] 40-pin qfn commercial, 0 to 70 c cy2sstv857lfc?32t [15] 40-pin qfn?tape and reel commercial, 0 to 70 c cy2sstv857zi?32 48-pin tssop industrial, ?40 to 85 c cy2sstv857zi?32t 48-pin tssop?tape and reel industrial, ?40 to 85 c cy2sstv857lfi?32 [15] 40-pin qfn industrial, ?40 to 85 c cy2sstv857lfi?32t [15] 40-pin qfn?tape and reel industrial, ?40 to 85 c ac electrical specifications (continued) [9, 10] parameter description condition min. typ. max. unit 857-32 0327l11 *swr# marketing part number date code and fab location lot code figure 7. actual marking on the device
cy2sstv857-32 document #: 38-07557 rev. *d page 8 of 9 ? cypress semiconductor corporation, 2003. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in do ing so indemnifies cypress semiconductor against all charges. package drawing and dimension all product and company names mentio ned in this document are the tradema rks of their respective holders. 1.100[0.043] 0.051[0.002] 0.851[0.033] seating plane 1 24 0.508[0.020] 0.500[0.019] 7.950[0.313] 0.25[0.010] 6.198[0.244] 12.395[0.488] 8.255[0.325] 5.994[0.236] 0.950[0.037] 0.500[0.020] bsc 12.598[0.496] 0.152[0.006] 0.762[0.030] 0-8 dimensions in mm[inches] min. max. max. 0.170[0.006] 0.279[0.011] gauge plane 0.20[0.008] 25 48 0.100[0.003] 0.200[0.008] reference jedec mo-153 package weight 0.33gms part # z4824 standard pkg. zz4824 lead free pkg. 48-lead (240-mil) tssop ii z4824 51-85059-*c 0.60[0.024] 5.70[0.224] 5.90[0.232] a c 1.00[0.039] max. n seating plane n 2 0.18[0.007] 0.50[0.020] 1 1 0.08[0.003] 0.50[0.020] 0.05[0.002] max. 2 (4x) c 0.24[0.009] 0.20[0.008] ref. 0.80[0.031] max. pin1 id 0-12 4.45[0.175] 6.10[0.240] 5.80[0.228] 4.55[0.179] 0.45[0.018] 0.20[0.008] r. dia. 0.28[0.011] 0.30[0.012] 0.60[0.024] 5.90[0.232] 5.80[0.228] 5.70[0.224] 6.10[0.240] 4.55[0.179] 4.45[0.175] top view bottom view side view e-pad (pad size vary by device type) 40-lead qfn 6 x 6 mm lf40a 51-85190-**
cy2sstv857-32 document #: 38-07557 rev. *d page 9 of 9 document history page document title: cy2sstv857-32 differential clock buffer/driver ddr400/pc3200-compliant, ddr400/pc3200-compliant document number: 38-07557 rev. ecn no. issue date orig. of change description of change ** 128403 08/04/03 rgl new data sheet *a 129080 09/05/03 rgl changed the maximum operating frequency from 200 mhz to 250 mhz added industrial temperature range changed the power supply from 2.5v to 2.6v changed the supply voltage from 2.38, 2. 5 and 2.63v to 2.3, 2.6 and 2.7v, respectively, in the dc electrical specifications table changed the fo value from 170 mhz to 200 mhz in the dc electrical spec- ifications table changed the duty cycle from 49.5 and 50.5 to 49 and 51% (60 to 170 mhz) changed the duty cycle from 49 and 51 to 48 and 52% (101 to 170 mhz) changed the half period jitter from 100 and 100 ps to 75 and 75 ps in the ac electrical specifications table *b 130114 10/28/03 rgl corrected qfn pinouts in the block diagram and in the pin description table *c 210076 see ecn rgl changed the operating frequency from 250 mhz to 230 mhz *d 259010 see ecn rgl changed half period jitter and propagation delay
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